Simulation

To verify the functionality of modified and new designs, we use Simulation tools that allow us to simulate the fabrication process of our sensors as well as their electrical properties. Furthermore, the influence of layout and fabrication parameters and variation on the device performance are accessible through simulations.

Simulations provide quantitative analysis of a new device before going into the actual fabrication, saving time and resources. Furthermore, simulations grant a look into the device helping to understand possible issues.

The simulations themselves are in principle finite element simulations, simply put, a set of equations is solved on a discrete grid. We utilize commercial and non-commercial tools. Synopsis TCAD as a standard tool for semiconductor simulations allows a variety of simulations as e.g. process and electrical simulations [1].  The tools TeSCA [2] and Oskar3 [3] have been developed by the WIAS [4] and provide reliable and fast device simulations either in addition or as alternative to Synopsis TCAD.

Using these tools, we are able to simulate a variety of quantities for our sensors. These range from the device processing over current-voltage characteristics to the process of charge collection and the simulation of impact ionization and the sensors noise.

In the following, we show some examples for simulations done with these different tools.

Synoposis TCAD 2D

Figure 2 shows an example for process and device simulations utilizing TCAD. In process simulations, all steps used in the fabrication of a silicon sensor can be simulated, from layer deposition, etching and oxidation to implantation and annealing steps. Figure 1 shows the result of a process simulation of a DePFET (Depleted P-channel Field Effect Transistor). The simulated structure is then used as input for electrical simulations. The distribution of the potential within the bulk (one of the results from electrical simulations) is shown in figure 1 on the right. A simulation of the transfercharacteristic, the dependence of the source current on the gate-source voltage, is shown in figure 2 on the left. To simulate the charge gain, first, charge is generated within the bulk for a time of about 50 ns (see figure 2 on the right). The charge is then collected in the internal gate. There it causes a change of the source-drain current.

Figure 1 Simulated structure and implantation profile for a DePFET transistor. The right shows the electrostatic potential within the bulk for a DePFET.

Figure 2 The left shows the source current with respect to the applied source-gate voltage at a fixed source-drain voltage. From the I-V characteristic, a suitable operation point can be extracted. The right shows a simulation for the charge gain. Charge is generated inside the bulk for about 50 ns. The charge is collected in the internal gate and modulates the source-drain current.

TeSCA 2D

An example for the simulation of the charge transfer in a CCD can be found in “Link to Rainers CCD Beitrag”

Synoposis TCAD 3D

Where two dimensional simulations allow a first check on simple devices or technology changes, three dimensional simulations are required for more complex devices. One example for 3D simulations done using TCAD is the Quadropix DePFETs shown in figure 3. Also the layout is showing an axis-symmetry, the applied potential causes an asymmetry within the device, that influences the splitting of charge between multiple pixels.

Figure 3 The left shows a scetch of the Quadropix layout. Also the layout is showing axis-symmetrie the asymmetric applied drain voltages lead to an asymmetric potential distribution within the bulk. To evaluate this and its influence on the device performance, three dimensional simulations are required.

Oskar3 3D

Another example where simple 2D simulations are not sufficient is the non-linear amplification of the DePFET for direct electron detection (“Link to EDET”). The layout of the EDET DePFET is shown in figure 4 on the right. The simulation covered a quarter of the overall layout as shown in figure 4 on the right.

Figure 4 The right shows the layout of the DePFERT for direct electron detection. Through the shape of the source implant a tailored non-linear signal response is achieved.

The layout implements an overflow region for the charge. First, charge is collected in the internal gate as normal. When a certain limit is reached, the charge starts to overflow into the first overflow region, as shown in figure 5 on the left. Only the charge in the internal gate causes a change of the DePFET current, the response of the sensor to the incident charge becomes smaller, i.e. non-liner as the right of figure 5 shows. To tailor this response, simulations have been carried out using Oskar3, in advance of the sensor production.

Figure 5 For an Edet DePFET two overflow regions (OR) have been implemented. On the left, the distribution of charge between the different region for the number of injected electrons is shown. Due to the tailored overflow regions, the response becomes non-linear as shown on the right. Due to the non-linear response, signals of up to 3 million electrons can be detected, while the resolution at small signals is still sufficient to provide good resolution for small signals.

References and furhter reading

1)      https://www.synopsys.com/silicon/tcad.html

2)      H. Gajewski et al, “TeSCA – Two Dimensional Semiconductor Analysis Package", Handbuch, WIAS, Berlin, "1997"

3)      K.Gärtner, J. Griepentrog and Th. Koprucki, User documentation Oskar3, Wias-Berlin, March 2011

4)      https://www.wias-berlin.de/software/index.jsp?id=TeSCA&lang=1

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